Semiconductor device and method for fabricating the same

ABSTRACT

A semiconductor device according to the present invention includes a semiconductor substrate, which comprises a first surface on which an electrode pad is formed, and a second surface arranged at an opposite side of the first surface; an external terminal formed on the first surface of the semiconductor substrate and is electrically connected to the electrode pad; and a sealing resin which seals the first surface so that a surface of the external terminal is exposed. An outer edge of the second surface has a chamfered portion, a surface of which is inclined by substantially 45 degrees from the second surface.

This is a Divisional of U.S. application Ser. No.: 11/220,921, filedSep. 8, 2005, the subject matter of which is incorporated herein byreference.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the priority of Application No. 2004-262398,filed on Sep. 9, 2004 in Japan, the subject matter of which isincorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor device and a method forfabricating the same. Especially, the present invention relates to asemiconductor device having an exposed rear or bottom surface and amethod for fabricating the same.

BACKGROUND OF THE INVENTION

Since mobile devices are getting smaller in size, and semiconductordevices used for such mobile devices are required to be smaller in sizeas well. In order to achieve such a request, a semiconductor devicecalled “chip size package”, having a dimension corresponding to asemiconductor chip, has been developed. Chip size package includes aWafer Level Chip Size Package and a Wafer Level Chip Scale Package(WCSP). A front or top surface of a semiconductor chip (semiconductorsubstrate) is sealed with a resin, while a rear or bottom surface, whichis a silicon surface, is exposed.

A WCSP is mounted on a mount board so that a front surface of thesemiconductor chip faces the mount board. In other words, a WCSP ismounted on a mount board so that a rear or bottom surface faces upward,as shown in Japanese Patent Publication No. 2003-60120A.

However, according to a WCSP described in the above publication, a rearsurface of a semiconductor chip is exposed, so that an edge chipping maybe occurred at an edge of the semiconductor chip when an external forceis applied thereto. The edge of the semiconductor chip may be broken.When a broken piece caused by an edge chipping phenomenon is stuck on toa mount board, short-circuit would be made. Now, it has been required toprevent such an edge chipping phenomenon from a WCSP.

OBJECTS OF THE INVENTION

Accordingly, an object of the present invention is to provide asemiconductor device in which an edge chipping phenomenon hardly occurs.

Accordingly, an object of the present invention is to provide a methodfor fabricating a semiconductor device in which an edge chippingphenomenon hardly occurs.

Additional objects, advantages and novel features of the presentinvention will be set forth in part in the description that follows, andin part will become apparent to those skilled in the art uponexamination of the following or may be learned by practice of theinvention. The objects and advantages of the invention may be realizedand attained by means of the instrumentalities and combinationsparticularly pointed out in the appended claims.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, a semiconductordevice includes a semiconductor substrate, which comprises a firstsurface on which an electrode pad is formed, and a second surfacearranged at an opposite side of the first surface; an external terminalformed on the first surface of the semiconductor substrate and iselectrically connected to the electrode pad; and a sealing resin whichseals the first surface so that a surface of the external terminal isexposed. An outer edge of the second surface has a chamfered portion, asurface of which is inclined by substantially 45 degrees from the secondsurface.

According to a second aspect of the present invention, a method forfabricating a semiconductor device includes: forming a groove on asecond surface of a semiconductor substrate, in which the semiconductorwafer comprises a first surface on which a plurality of semiconductordevices are formed and segmented by a dicing line and a second surfacearranged at an opposite side of the first surface, the groove is formedalong the dicing line, the groove has a inclined surface with a firstwidth which gets narrower toward the first surface; and dicing thesemiconductor wafer along the dicing line with a dicing blade having asecond width, which is narrower than the first width.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plane perspective view illustrating a rear or bottom surfaceof a semiconductor device 101 according to a first preferred embodimentof the present invention.

FIG. 2 is a schematic cross-sectional view taken on line 2-2 in FIG. 1.

FIG. 3 is a plane perspective view illustrating a front or top surfaceof a semiconductor device 101 according to the first preferredembodiment.

FIG. 4 is a schematic cross-sectional view taken on line 4-4 in FIG. 3.

FIG. 5 is a plane view illustrating a mount board 501 on which thesemiconductor device 101 according to the first preferred embodiment isto be mounted. FIG. 6 shows mounting steps of the semiconductor device101 on the mount board 501.

FIG. 7 shows fabricating steps of the semiconductor device 101 accordingto the first preferred embodiment.

FIG. 8 shows fabricating steps of the semiconductor device 101 accordingto the first preferred embodiment.

FIG. 9 shows fabricating steps of the semiconductor device 101 accordingto the first preferred embodiment.

FIG. 10 shows a first step for fabricating the semiconductor device 101.

FIG. 11 is a plane view illustrating a front surface of a semiconductorwafer 1101.

FIG. 12 shows a second process for fabricating the semiconductor device101.

FIG. 13 is a schematic cross-sectional view corresponding to anencircled region “A” shown in FIG. 12(D).

FIG. 14 is a cross-sectional view illustrating a blade used in the firstpreferred embodiment.

FIG. 15 is a rear surface of the semiconductor wafer 1101, correspondingto the step shown in FIG. 12(D).

FIG. 16 shows fabrication steps of the semiconductor device 101according to another embodiment of the present invention.

FIG. 17 is a schematic cross-sectional view of another embodiment,corresponding to an encircled region “A” shown in FIG. 12(D).

FIG. 18 is a schematic cross-sectional view of another embodiment,corresponding to an encircled region “A” shown in FIG. 12(D).

DETAILED DISCLOSURE OF THE INVENTION

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings which form a part hereof,and in which is shown by way of illustration specific preferredembodiments in which the inventions may be practiced. These preferredembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother preferred embodiments may be utilized and that logical, mechanicaland electrical changes may be made without departing from the spirit andscope of the present inventions. The following detailed description is,therefore, not to be taken in a limiting sense, and scope of the presentinventions is defined only by the appended claims.

Now, preferred embodiments of the present invention will be described.In the attached drawings, the same or corresponded elements arerepresented by the same reference numerals.

FIG. 1 is a plane perspective view illustrating a rear or bottom surfaceof a semiconductor device 101 according to a first preferred embodimentof the present invention. FIG. 2 is a schematic cross-sectional viewtaken on line 2-2 in FIG. 1.

A semiconductor device 101 includes a semiconductor substrate 103(semiconductor chip); a sealing resin 111 and a plurality of projectedelectrodes 113. As shown in FIGS. 1 and 2, the semiconductor device 101is shaped to have the same outside dimension as the semiconductor chip103. According to the embodiment, the semiconductor device 101 isdesigned, for example, to be a square of 8 mm by 8 mm.

The semiconductor substrate 103 includes a front surface (firstprincipal surface) 109 on which a circuit element is formed; a rearsurface 105 (second principal surface) provided at the opposite side ofthe front surface 109; and a plurality of side surfaces extending andarranged between the front surface 109 and the rear surface 105. Thefront surface 109 could be called an upper surface and the rear surface105 could be called a lower surface. The semiconductor substrate 103further includes a chamfered portion 107 formed on an edge of the rearsurface 105. The chamfered portion 107 also can be called inclinedportion. The chamfered portion 107, which is one of the features of thepresent invention, is formed along a peripheral region of the rearsurface 105 surrounding a center region (inner region) thereof. In otherwords, the chamfered potion 107 is along first to fourth side surfaces115, 117, 119 and 121 The first and second side surfaces 115 and 117 areopposing to each other. The third and fourth side surfaces 119 and 121are opposing to each other. Each of the third and fourth side surfaces119 and 121 is positioned next to the first and second side surfaces 115and 117.

The sealing resin 111 is formed on the front surface 109 of thesemiconductor substrate 103. The sealing resin 111 functions to protectcircuit elements, not shown, formed on the front surface 109 fromexternal environment. The plurality of projected electrodes 113 areformed on posts, which is not shown but arranged inside the sealingresin 111. The plurality of projected electrodes 113 are electricallyconnected to circuit elements on the semiconductor substrate 103 via theposts. The details of such posts will be described later. The projectedelectrodes 113 function as external terminals of the semiconductordevice 101.

FIG. 3 is a plane perspective view illustrating a front or top surfaceof a semiconductor device 101 according to the first preferredembodiment. FIG. 4 is a schematic cross-sectional view taken on line 4-4in FIG. 3.

In FIG. 3, electrode pads 301, a metal wiring layer 303 and theprojected electrodes 113 are illustrated. Since the electrode pads 301and the metal wiring layer 303. is arranged on a layer lower than thesealing resin 111, the electrode pads 301 and the metal wiring layer 303are illustrated by broken lines in FIG. 3.

As shown in FIG. 3, sixteen electrode pads 301 are formed with a 100micro meters (100 μm) interval or space at a peripheral region of thetope surface 109 of the semiconductor substrate 103. Sixteen projectedelectrodes 113 are formed in a matrix or grid manner at a center region(inner region) of the front surface 109 of the semiconductor substrate103. Each of the projected electrodes 113 is electrically connected to acorresponding metal wiring layer 303 via a post, not shown.

The metal wiring layer 303 functions substantially to shift a positionof an external terminal from the peripheral region to the center regionof the semiconductor substrate 103. In general, such position shift iscalled “re-positioning” or “re-arrangement”, and the metal wiring layer303 can be called “re-positioning wiring” or “re-wiring”. As describedabove, since the projected electrodes 113 functioning as externalterminals are arranged at the center region of the semiconductorsubstrate 103, a mount board to be connected to the semiconductor devicecan be smaller in size.

Next, the detailed structure of the semiconductor device 101 will bedescribed in reference to FIG. 4.

A plurality of circuit elements, not shown, are formed on the frontsurface 109 (first principal surface) of the semiconductor substrate103, which is made of silicon. The chamfered potion 107 is provided onthe rear surface 105 (second principal surface) of the semiconductorsubstrate 103. An insulating layer 402, having contact holes, is formedon each circuit element. A conductive layer, not shown, is formed insidethe contract holes.

The electrode pads 301 are formed on the insulating layer 402. Theelectrode pads 301 are electrically connected to circuit elements viathe conductive layer formed in the contact hole. For example, theelectrode pads 301 may be made of aluminum containing silicon.

An interlayer insulating film (layer) 403 is formed on a passivationlayer (film) 401. The interlayer insulating film 403 reduces stressapplied to the semiconductor substrate 103. The interlayer insulatingfilm 403 may be made of polyimide. It should be noted that a surface ofthe interlayer insulating film 403 that is positioned directly below ametal thin-film layer 405 transmuted or deteriorated. Such transmutedregion is illustrated by a bold line in FIG. 4. The transmuted region ofthe interlayer insulating film 403 improves adhesiveness between theinterlayer insulating film 403 and the metal thin-film layer 405.

The metal thin-film layer 405 is formed on the interlayer insulatingfilm 403 and the electrode pads 301. The metal thin-film layer 405 canbe of a single layer structure or multi-layered structure. Preferably,the metal thin-film layer 405 is of a multi-layered structure, includingupper and lower layers. The lower layer is made of a material which hasa good adhesiveness to the electrode pads 301 and can prevent that amaterial including in the upper layer is diffused into the semiconductorsubstrate 103. Such a lower layer may be made of titanium. The upperlayer is made of a material which has a good adhesiveness to the metalwiring layer 303. Such an upper layer may be made of copper.

The metal wiring layer 303 is formed on the metal thin-film layer 405.The metal wiring layer 303 may be made of copper. Posts 407 are formedon a surface of the metal wiring layer 303. According to thisembodiment, the posts 407 are shaped about cylindrical or column. Anrear surface of the post 407 is in contact with the surface of the metalwiring layer 303, a top end of the post 407 is in contact with theprojected electrode 113. The posts 407 are made of the same material asthe metal wiring layer 303 to have a height, a distance between thesurface of the metal wiring layer 303 and the surface of the sealingresin 115, of 100 micro meters (100 μm).

The sealing resin 115 is formed over the upper surface 109 of thesemiconductor substrate 103 entirely to cover the upper surface 109except top ends of the posts 407. In other words, the sealing resin 115covers the interlayer insulating film 403, the metal thin-film layer405, the metal wiring layer 303 and side surfaces of the posts 407. Anupper surface of the sealing resin 115 and the top ends of the posts 407are arranged in the same horizontal level. The sealing resin 115 may beof an opaque epoxy resin.

The projected electrodes 113 are formed on the top ends of the posts407. The projected electrodes 113 are electrodes to be connected to awiring formed on a mount board, which is not shown. Circuit elementsformed on the semiconductor substrate 103 are electrically connected toan external device via the metal wiring layer 303, the posts 407 and theprojected electrodes 113. The projected electrodes 113 may be made ofsolder. Each of the projected electrodes 113 is shaped semi-spherehaving a diameter of 400 micro meters (400 μm).

Next, mounting process of the semiconductor device 101 to a mount board501 will be described in connection with FIGS. 5 and 6.

FIG. 5 is a plane view illustrating a mount board 501 on which thesemiconductor device 101 according to the first preferred embodiment isto be mounted.

The mount board 501 includes a plurality of terminals 505, which arearranged in a matrix or grid manner at positions corresponding to theprojected electrodes 113. The terminals 505 include a specific terminal509, which is called first terminal for an address signal A1.

Each of the terminals 505 is connected to a corresponding wiring 507.The wirings 507 may be connected other devices mounted on the mountboard 501. A device mounting area 503 is shown by broken line in FIG. 5.The semiconductor device 101 is to be mounted at the mounting area 503.The broken line also shows a dimension of the semiconductor device 101.

FIG. 6 shows mounting steps of the semiconductor device 101 on the mountboard 501.

The plurality of projected electrodes 113 of the semiconductor device101 include a specific projected electrode 114, which is an externalterminal called a first pin and is used, for example, for an addresssignal A1. A WCSP semiconductor device 101 would be stored once on atape-and-reel or tray after the device is taken out of the semiconductorwafer. For the later mounting process, the semiconductor devices 101would be equalized in direction on a tape-and-reel or tray in a certainmanner. For example, the semiconductor devices 101 are stored on atape-and-reel, so that each first pin 114 is arranged at a left lowerarea of the corresponding semiconductor device 101.

The semiconductor device 101 may be carried to a tape-and-reel using anauto handler with an image recognition apparatus. A first pin mark, notshown, is provided adjacent the first pin 114 on the rear surface 105.The auto handler detects and recognizes the position of the first pinmark and carries the semiconductor devices 101 to the tape-and-reel sothat all first pins 114 are arranged at left lower areas of thesemiconductor devices 101.

As described above, the semiconductor device 101 is taken out of thetape-and-reel by an automatic mounting apparatus with an imagerecognition device. The automatic mounting apparatus recognizesdirections of the semiconductor devices 101, since the automaticmounting apparatus equipping an image recognition device. As shown inFIG. 6(a), the semiconductor device 101 is carried above the mount board501 by the automatic mounting apparatus. At this time, the semiconductordevice 101 is arranged to face the mount board 501 so as that the firstpin 114 and the first terminal 509 are directly facing each other.

Next, as shown in FIG. 6(b), the projected electrodes 113 of thesemiconductor device 101 are connected to a plurality of terminals 505on the mount board 501, and the mounting process is completed.

Now, a method for fabricating a semiconductor device (101) according toa first aspect of the present invention is described. For easyunderstanding, the fabrication process is described by two differentprocesses. A first process includes steps until projected electrodes 113are formed, before a dicing process of a semiconductor wafer. The restof the process is called a second process. The first process isillustrated in FIGS. 7 through 10, since the second process isillustrated in FIGS. 12 through 14.

For easy understanding, the first process is described only for a regiontaken on line 4-4 in FIG. 3.

First, a plurality of circuit elements are formed on a front surface 109(first principal surface) of a semiconductor substrate 103, which is asemiconductor wafer. Next, an insulating layer 402 is formed on each ofthe circuit elements. The insulating layer is provided with contactholes therein, which is not shown. A conductive layer, not shown, isformed in the contact hole. Subsequently, an aluminum layer, containingsilicon, is formed on the insulating layer 402 by a sputtering process.After that, the aluminum layer is etched to be a specific shape so thatan electrode pad 301 is formed on the insulating layer 402. Theelectrode pad 301 is connected to the conductive layer, formed insidethe insulating layer 402, as shown in FIG. 7(A).

A passivation layer 401, which is of a silicon nitride, is formed on theinsulating layer 402 and the electrode pad 301 by a CV process. Afterthat, the passivation layer 401 positioned on a center region of theelectrode pad 301 is selectively etched and removed, as shown in FIG.7(B).

Next, an interlayer insulating layer 403, which is of polyimide, isformed on the passivation layer 401 and the electrode pad 301, as shownin FIG. 7(C). Next, the interlayer insulating layer 403 positioned on acenter region of the electrode pad 301 is selectively etched andremoved, as shown in FIG. 7(D).

Subsequently, the interlayer insulating layer 403, which is made ofpolyimide, is heated for thermosetting. As shown in FIG. 7(E), thedrawing, the interlayer insulating layer 403 positioned above theelectrode pad 301 is tapered to have an inclined region by thethermosetting process. If some polyimide is remained on the electrodepad 301, the remained polyimide is removed by a plasma etching processin oxygen atmosphere (FIG. 7(E)).

A plasma etching process is applied to the interlayer insulating layer403 in an inert gas, such as argon, so as to transmute a surface of theinterlayer insulating layer 403, as shown in FIG. 7(F). The transmutedsurface is shown by a bold line in the drawings. The transmuted surfaceimproves adhesiveness with a metal thin-film 405 (FIG. 7(F)). The metalthin-film layer 405 is formed on the interlayer insulating layer 403 andthe electrode pad 301 by a sputtering process, as shown in FIG. 7(G).

Next, a resist 801 is formed on the metal thin-film layer 405 to have athickness, for example, of 10 micro meters (10 μm). After that, theresist 801 is selectively removed by an etching process, as shown inFIG. 8(A).

Subsequently, a metal wiring layer 303 is selectively formed on anexposed region of the metal thin-film layer 405 by an electro platingprocess, as shown in FIG. 8(B). The metal wiring layer 303 has athickness, for example, of 5 micro meters (5 μm) which is thinner thanthat of the resist 801.

Next, the resist 801 is removed using a peeling agent, such as acetone,as shown in FIG. 8(C). Next, another resist 803 having a thickness ofabout 120 micro meters (120 μm) is formed on the metal thin-film layer405 and the metal wiring layer 303, as shown in FIG. 8(D). After that,the resist 803 is selectively removed from an area above a post formingregion 805, as shown in FIG. 8(D).

Subsequently, a post 407 is formed in the post forming region 805 by anelectro plating process, as shown in FIG. 8(E). The post 407 has athickness of about 100 micro meters (100 μm), which is thinner than thatof the resist 803. The post 407 may be made of the same material as thatmetal wiring layer 303, so that the same plating solution used forforming the metal wiring layer 303 could be used for forming the post407.

Next, the resist 803 is removed using a peeling agent, as shown in FIG.9(A). Next, an exposed portion of the metal thin-film layer 405 isremoved by a plasma etching process in an oxygen atmosphere, as shown inFIG. 9(B). After that, an exposed surface of the interlayer insulatinglayer 403 is removed by a wet etching process, as shown in FIG. 9(C), sothat it is prevented that an electric current flowing through a metalwiring layer (303) is leaked to another metal wiring layer (303) via thesurface of the interlayer insulating layer 403.

Next, the whole semiconductor wafer is set in a sealing mold (die),which is not shown, then a sealing resin is injected into the mold, sothat a sealing resin 115 is formed on a upper surface 109 of thesemiconductor substrate 103, as shown in FIG. 9(D). The sealing resin115 covers the interlayer insulating layer 403, the metal thin-filmlayer 405, the metal wiring layer 303 and a side surface of the post407.

Subsequently, a surface of the sealing resin 115 is polished to exposean upper surface of the post 407. The upper surface of the post 407 andthe surface of the sealing resin 115 are in the same horizontal level(the same plane).

Next, a projected electrode 113 is formed on the upper surface of thepost 407 by a screen printing process, as shown in FIG. 10. Theprojected electrode 113 is shaped semi-sphere having a diameter of 400micro meters (μm).

An upper surface of the above-processed semiconductor wafer 1101 isshown in FIG. 11. A plurality of semiconductor devices 101, which are tobe diced and separated in the second process, are formed on thesemiconductor wafer 1101. The semiconductor devices 101 are segmentedand separated from each other by a plurality of scribe regions 1103. Atthis stage, chamfered portions 107 have not been formed on thesemiconductor devices 101, and a bottom (lower) surface of thesemiconductor wafer is not shown here.

Now, the second process following the above-described first process isdescribed in connection with FIG. 12. FIG. 12 shows the second processfor fabricating the semiconductor device 101. For easy understanding ofthe present invention, some regions and components are omitted in FIG.12.

FIG. 12(A) shows an intermediate product after the first process, shownin FIGS. 7 to 10. As shown in FIG. 12(A), the interlayer insulatinglayer 403, the metal wiring layer 303, the posts 407 and projectedelectrodes 113 are formed on the semiconductor wafer 1101.

A wafer holder 1203, having a wafer ring 1205 and a dicing sheet 1207,is prepared. The wafer ring 1205 is shaped to be circle and ring. Forexample, the dicing sheet 1207 may be a UV tape, having a characteristicin which an adhesive strength would be lowered when ultraviolet rays isirradiated thereto. The semiconductor wafer 1101 is adhered onto thedicing sheet 1027 so that the projected electrodes 113 are in contactwith the dicing sheet 1207, as shown in FIG. 12(B).

Next, the wafer holder 1203 is mounted on a grinder having a pair ofdiamond grindstones 1209, as shown in FIG. 12(C). A first diamondgrindstone has a roughness of #325 and a second diamond grindstone 1209has a roughness of #2000. A bottom or lower surface of the semiconductorwafer 1101 is grinded or polished as follows: Firstly, the rear surfaceof the semiconductor wafer 1101 is roughly grinded with the firstdiamond grindstone, and then is finely grinded with the second diamondgrindstone 1209. The semiconductor wafer 1101 is grinded until the wafer1101 has a thickness of about 310 micro meters (μm).

The rear surface of the semiconductor wafer 1101 is polished with thesecond diamond grindstone 1209 so that the rear surface becomes in acondition of mirror finish. The rear surface of the semiconductor wafer1101 is required to be polished finely. That is because, if the rearsurface of the semiconductor wafer 1101 is not fine enough and rough, itwould be difficult that the scribe regions are detected by an infraredcamera.

Next, the semiconductor wafer 1101 with the wafer ring 1203 is mountedon a dual dicing apparatus equipped with an infrared camera 1211, asshown in FIG. 12(D). The dual dicing apparatus, which is not shown inthe drawings, is provided with a couple of blades arranged in parallelto each other. First and second blades 1410 and 1420 used in thisembodiment are illustrated in FIG. 14(a) and (b), respectively.

The first blade 1410 includes an inclined surface 1440 and a sidesurface 1430. The inclined surface 1440 extends continuously from theside surface 1430 to be inclined substantially 45 degrees from ahorizontal line. The first blade 1410 is shaped to have a width of 200micro meters (200 μm). The width can be said a distance between theopposing two side surfaces 1430. The width of the first blade 1410 canbe changed, for example, of 100 to 300 micro meters (100-300 μm) inaccordance with a depth of groove to form. The inclined surface 1440 hasa roughness of #2000.

The second blade 1420 is shaped to have a cross section of about squareor rectangular and a width of 30 micro meters (30 μm). The width can besaid a distance between opposing two side surfaces 1450. The width ofthe second blade 1420 can be changed, for example, of 30 to 50 micrometers (30-50 μm). The second blade 1420 may have a roughness of #2000.

FIG. 13 is a schematic cross-sectional view corresponding to anencircled region “A” shown in FIG. 12(D). A width of the scribe region1103 is lo determined to be about 80 micro meters (80 μm). A distancebetween an edge of the scribe region 1103 and an edge of the electrodepad 301 is determined to be about 50 micro meters (50 μm). A scribe line1301 has a width of 30 micro meters (30 μm), which is almost the same asthe width of the second blade 1420.

In the process shown in FIG. 12(D), a V-shape groove 108 is formedwithin a range of 150 micro meters (150 μm), including the center linedof the scribe region 1103. The V-shape groove 108 formed on the rearsurface 105 of the semiconductor wafer 1101 has a width of about 150micro meters (150 μm), which is narrower than the width of the firstblade 1410, and a depth of about 75 micro meters (75 μm). The V-shapegrooves 108 are formed with the inclined surface 1440 of the first blade1410. The side surfaces 1140 of the first blade 1410 are not used toform the V-shape grooves 105. The shape of the groove 108 corresponds tothe shape of the inclined surfaces 1440 of the first blade 1410, shownin FIG. 14(a). Each of the V-shape grooves 108 has an inner inclinedsurface, which is inclined by substantially 45 degrees from the rearsurface 105 of the semiconductor wafer 1101. The interior angle of theV-shape grooves 108 may have an error of ±5 degrees from the optimumdesigned value of 45 degrees due to manufacturing tolerance or margin ofthe blade and a cutting error.

As shown in FIG. 12(D), the pattern shape of the plurality of electrodepads 301 or the metal wiring layer 303, formed on the upper surface ofthe semiconductor wafer 1101 is detected and recognized from the rearsurface of the semiconductor wafer 1101 by the infrared camera 1211. Thedicing apparatus recognizes the position of the scribe regions 1103formed on the upper surface 109 of the semiconductor wafer 1101.

Next, the first blade 1410 is arranged above the center line of thescribe region 1103. After that, the rear surface 105 of thesemiconductor wafer 1101 is grinded by about 150 to form the V-shapegrooves 108, as shown in FIG. 13. Such a grinding process with the firstblade 1410 is carried out to all of the scribe regions 1103. In otherwords, the grinding process with the first blade 1410 is carried out toevery four sides of each of the semiconductor devices 101.

FIG. 15 is a rear surface of the semiconductor wafer 1101, correspondingto the step shown in FIG. 12(D). It can be understood from FIG. 15 thata chamfered portion 107 is formed at every four sides of thesemiconductor device 101 using the first blade 1410.

Next, the second blade 1420 is positioned above the center line of ascribe region 1103, that is the scribe line 1301. After that, the rearsurface 105 of the semiconductor wafer 1101 is grinded with the secondblade 1420 along the scribe line 1301 by a depth of 400 micro meters(400 μm). In other words, a full cutting process is carried out to thesemiconductor wafer 1101. The grinding process with the second blade1420 is carried out to every semiconductor devices 1101 to separate thesemiconductor devices 101 from each other, as shown in FIG. 12(E).

Next, the semiconductor wafer 1101 with the dicing sheet 1207 istransferred to an expand-ring. After that, the dicing sheet 1207 isexposed to an ultraviolet ray to decrease its adhesiveness. The dicingsheet 1207 is expanded toward the outer edge of the semiconductor wafer,and each semiconductor device 101 is taken out by a collet.

According to the above described processes, the semiconductor device101, shown in FIGS. 1 and 2, is completed.

The present invention includes features not only on a semiconductordevice itself but also on a fabrication method. According to the presentinvention, the V-shape grooves 108 are formed before each semiconductordevice 101 is separated from the other semiconductor devices. Thesemiconductor device 101 having the chamfered portion 107 can be easilyfabricated by adding a process of forming the V-shape groove 108 withthe first blade.

According to the present embodiment, as shown in FIG. 13, the chamferedportion 107 has a depth of 60 micro meters (60 mμ) in a directionparallel to a thickness direction of the semiconductor device 101. Ifthe depth of the chamfered portion 107 is too much, circuit elementsformed on the front surface 109 of the semiconductor chip 103 may wouldbe affected negatively. On the other hand, if the depth of the chamferedportion 107 is not deep enough, an edge chipping phenomenon could not beprevented effectively. For those reasons, the depth of the chamferedportion 107 is preferably determined in a range of 50 to 150 micrometers (50-150 μm). The depth of the chamfered portion 107 is preferablydetermined in a range of 15% to 45% of the thickness of thesemiconductor wafer 1101.

The semiconductor wafer 1101 may be grinded with the second blade 1420and separated from a side on which the sealing resin 111 is formed, asshown in FIG. 16(E). In this case, even if the second blade 1420 isslightly shifted from the V-shape groove 108, slippage of the secondblade 1420 could be suppressed. Further, as shown in FIG. 17, an edge1710 of the V-shape groove 108 may be blunted or smoothed. The bluntingor smoothing process can be carried out by a wet etching technique.

As shown in FIG. 18, a groove 1810 can be formed by a laser processinstead of forming the V-shape groove 108 with the first blade 1410. Inthe case of forming a groove with a laser, a region of the semiconductorsubstrate 1101 to which the laser is irradiated is melted, so that achipping tolerance is improved.

1. A semiconductor device, comprising: a semiconductor substrate, whichcomprises a first surface on which an electrode pad is formed, and asecond surface arranged at an opposite side of the first surface; anexternal terminal formed on the first surface of the semiconductorsubstrate and is electrically connected to the electrode pad; and asealing resin which seals the first surface so that a surface of theexternal terminal is exposed, wherein an outer edge of the secondsurface has a chamfered portion, a surface of which is inclined bysubstantially 45 degrees from the second surface.
 2. A semiconductordevice according to claim 1, wherein the chamfered portion is formed tohave a depth from the second surface of 50 to 150 μm (micro meters). 3.A semiconductor device according to claim 2, further comprising: arewiring extending from the first surface, in which one end of therewiring is connected to the electrode pad and the other end isconnected to the external terminal.
 4. A semiconductor device accordingto claim 3, further comprising: a ball electrode provided on the surfaceof the external terminal, which is exposed from the sealing resin.
 5. Asemiconductor device according to claim 1, wherein the external terminalis a post electrode, which comprises a side surface covered with thesealing resin and a top surface exposed from the sealing resin. 6-19.(canceled)